This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-322548, filed Nov. 12, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a read circuit which read data stored in a memory cell, nonvolatile semiconductor memory device having an improved read method, and a control method thereof.
Nonvolatile memory (EEPROM) is widely known as semiconductor memory which retains data written in a memory cell with no power voltage supplied. A type of nonvolatile memory, called flash memory, can electrically erase data in a plurality of memory cells collectively.
FIG. 1 shows a schematic configuration of conventional flash memory. Each cell contains a bit line BL and a word line WL. FIG. 1 shows just two BLs BL0 and BL1 and two WLs WL0 and WL1. Each intersection is provided with memory cell MC comprising nonvolatile transistor, namely an FETMOS-structured transistor having a floating gate. Bit lines BL0 and BL1 and word lines WL0 and WL1 in a plurality of cells and a plurality of memory cell MCs constitute a memory cell array.
Each memory cell in a memory cell array comprises a source, a drain, a floating gate, and a control gate. Drains for memory cell MCs arranged on the same column (Y-axis direction) are commonly connected to a bit line in each cell for the corresponding columns. Control gates for memory cell MCs arranged on the same row (X-axis direction) are commonly connected to a word line for the corresponding rows. Sources for memory cell MCs are commonly connected to a source line SL in a given unit.
An X decoder (row decoder) 101 selects one of a plurality of the word lines (row selection). A Y decoder (column decoder) 102 selects one of a plurality of the bit lines in each cell.
A read circuit 103 senses data by reading data stored in a cell selected by the X decoder 101 and the Y decoder 102. The read circuit 103 comprises a bit line BLL to which a cell-based bit line selected by Y decoder 102 is connected, a sense bit line BLS, a separation circuit 105, a bias circuit 107, a load circuit 109, a sense line SA, and an amplifier circuit 110. The separation circuit 105 comprises an N-channel separation transistor 104. The separation transistor 104 is connected between the bit line BLL and the sense bit line BLS and electrically separates between the sense bit line BLS and the bit line BLL. The bias circuit 107 comprises an N-channel bias transistor 106. The bias transistor 106 is connected between the sense bit line BLS and the sense line SA and optimizes voltages for memory cell MC""s drains (the bit line BLL and the cell-based bit line BL) when data is read. The load circuit 109 uses a transistor 108 for a P-channel load which sets the sense line SA to a power supply voltage Vcc when data is read. During a sense period, the amplifier circuit 110 senses data by comparing a voltage generated on the sense line SA with a specified reference voltage VREF generated in a circuit (not shown).
The separation transistor 104""s gate is supplied with a control signal PART. The bias transistor 106""s gate is supplied with a bias voltage VBIAS which is lower than the power supply voltage Vcc.
The following describes a data read operation in the flash memory having the above-mentioned configuration with reference to a timing chart in FIG. 2. As shown in FIG. 2, data is read in three basic periods: an address selection period, a sense period, and an output period.
The address selection period takes effect from when an external address change is received until the word line and the cell-based bit line are selected in a memory cell array. During this period, it is necessary to stabilize a bias voltage VBIAS supplied to the bias transistor 106""s gate. When the bias voltage VBIAS does not reach or exceeds a stable level during this period, the so-called soft-write effect occurs. By contrast, when the bias voltage VBIAS is lower than a stable level, bit line BLL charging delays. This is because the bias transistor 106 clamps the bit line BLL""s voltage to a value which is lower than Vcc.
During the next sense period, the control signal PART turns on the separation transistor 104 and activates the amplifier circuit 110 at a timing when a memory cell is selected from the memory cell array. Before the separation transistor 104 turns on, a reset circuit (not shown) sets the bit line BLL to 0V. When the separation transistor 104 turn on, the bit line BLL becomes charged. Thereafter, a voltage VBLL of the bit line BLL varies with data stored for the selected memory cell. When the selected memory cell is set to xe2x80x9c0xe2x80x9d, this memory cell does not turn on even if the word line is selected and is activated. The VBLL rises to a high voltage. By contrast, when the selected memory cell is set to xe2x80x9c1xe2x80x9d, selecting the word line turns on this memory cell. The voltage VBLL lowers compared to the case where the data is set to xe2x80x9c0xe2x80x9d.
When the amplifier circuit 110 is activated, a sense line SA voltage VSA is compared with the reference voltage VREF to sense data for the selected memory cell. At this time, the reference voltage VREF is approximately set to a middle between a bit line BLL voltage when data is read from the memory cell set to xe2x80x9c1xe2x80x9d and a bit line BLL voltage when data is read from the memory cell set to xe2x80x9c0xe2x80x9d.
During the output period, data latched by the amplifier circuit 110 is sensed. This latched data is sent to an output circuit (not shown) and is output from an output pad (not shown).
As shown in FIG. 2, the bias voltage VBIAS stabilized after the address change temporarily drops when the sense period starts. The reason is described below.
FIG. 3 provides an enlarged view of changes in voltages VBLL and VSA for the bit line BLL and the sense line SA during the address selection period and the sense period with reference to a change of the bias voltage VBIAS in FIG. 2.
The bit line BLL voltage VBLL is set to 0V when the control signal PART is activated and the separation transistor 104 turns on. The bit line BLL voltage VBLL is first charged when the sense period starts and the separation transistor 104 turns on.
The sense line SA voltage VSA is stable with a given value (Vccxe2x88x92Vthp) till the sense period, where Vthp is a threshold value of a P-channel MOS transistor. When the sense period starts, the sense line SA voltage VSA drastically drops. This is because turning on the separation transistor 104 charges a large capacity parasitically given to the bit line BLL. Accordingly, the sense line SA voltage VSA drops down to almost the same level as the bit line BLL voltage VBLL. The bias voltage VBIAS temporarily drops under the influence of this bit line voltage drop.
This is described in more detail with reference to equivalent circuit diagrams in FIGS. 4A through 4D. FIG. 4A shows each transistor state and each node voltage state at a final stage of the address selection period. The bit line BLL remains set and maintains its voltage VBLL to 0V. The sense line SA remains in an initial state and maintains its voltage VSA to (Vccxe2x88x92Vthp). The bias voltage VBIAS already reaches a stable state. The load transistor 108 charges the sense bit line BLS approximately up to (VBIASxe2x88x92Vth), where Vth is a threshold value of the bias transistor 106. At this time, the bias transistor 106""s source voltage (VBLS) rises to (VBIASxe2x88x92Vth) which turns off the bias transistor 106 itself. Accordingly, the bias transistor 106 remains off. Since the control signal PART is inactive, the separation transistor 104 is also off.
FIG. 4B shows each transistor state and each node voltage state when the sense period starts. When the control signal PART is activated and the separation transistor 104 turns on, an electric charge accumulated for the sense line SA and the sense bit line BLS is shared with a large capacity CBLL on the bit line BLL. At this time, the voltages VSA and VBLS for the sense line SA and the sense bit line BLS each drop down to almost 0V from the states in FIG. 4A. As shown in FIG. 4C, the bias voltage VBIAS decreases under the influence of coupling due to a gate-drain capacity Cgd and a gate-source capacity Cgs for the bias transistor 106. Consequently, the bias voltage VBIAS temporarily drops.
The bias transistor 106 is off in FIG. 4A, but turns on in FIG. 4B because the source voltage becomes 0V. The bias transistor 106 forms a channel and provides a large channel capacity for the gate. When the bias transistor 106 is on, it is assumed to be a large capacity as shown in FIG. 4D. The bias voltage VBIAS charges this capacity. Accordingly, turning on the bias transistor 106 and charging a channel capacity also causes the bias voltage VBIAS to drop.
If the bias voltage VBIAS cannot maintain a sufficiently high voltage during the sense period, the bit line BLL is charged too late, delaying the read time. In a worst case, a read error occurs.
If the once stabilized bias voltage VBIAS decreases, it needs to be increased to resume the stable state. An unnecessary current is consumed for a circuit which generates this bias voltage VBIAS.
In addition to FIG. 1, FIGS. 5, 6, and 7 show other schematic configurations of read circuits for the conventional flash memory.
The read circuit in FIG. 5 is void of the load circuit 109. Instead, the bias circuit 107 has a function equivalent to the load circuit 109. Such a read circuit is disclosed, say, in Japanese Patent Application No. 11-164183.
Also for the read circuit in FIG. 5, the sense bit line BLS is charged before the sense period. Thereafter, turning on the separation circuit 105 charge-shares with a large capacitance on the bit line BLL, causing the same problem as for the read circuit in FIG. 1.
The read circuit in FIG. 6 is void of the separation circuit 105. Instead, the Y decoder 102 has a function equivalent to the separation circuit 105. The separation circuit 105 is activated at a timing when the Y decoder 102 is activated. Consequently, the Y decoder 102 also functions like the separation circuit 105.
The read circuit in FIG. 6 also charges the bit line BLL before the sense period. Thereafter, turning on the Y decoder 102 charge-shares with a capacitance on the bit line BLL, causing the same problem as for the read circuit in FIG. 1. Basically, the cell-based bit line BL provides more capacitance than the bit line BLL. A smaller bit line BLL capacitance is charge-shared with a larger cell-based bit line BL capacitance due to column selection by the Y decoder 102.
The read circuit in FIG. 7 is void of the separation circuit 105 and the load circuit 109 in FIG. 1. Instead, the bias circuit 107 has a function equivalent to the load circuit 109 in FIG. 1. The Y decoder 102 has a function equivalent to the separation circuit 105 in FIG. 1.
Also regarding the read circuit in FIG. 7, the bias voltage VBIAS supplied to the bias circuit 107 temporarily drops when the sense period starts.
Conventionally, as mentioned above, the read circuit is provided with a bias circuit for preventing a soft-write effect by setting a memory cell""s drain voltage to a value lower than a power supply voltage when data is read. The bias circuit is supplied with a bias voltage which temporarily drops at the beginning of the sense period. This voltage drop causes problems such as a delayed read time, a read error, and an increased current consumed.
Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device and a control method thereof for preventing a delayed read time, a read error, and an increased current consumed by always stabilizing a bias voltage supplied to a bias circuit in a read circuit.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array having cell-based bit lines and nonvolatile memory cells connected thereto, the nonvolatile memory cell is selected according to address signals in an address selection period; a bit line to which a signal voltage of the cell-based bit line is transmitted; a cell-based bit line decoder circuit for connecting the cell-based bit line in the memory cell array to the bit line in the address selection period according to the address signal; a sense bit line to which a signal voltage of the bit line is transmitted; a separation circuit connected between the sense bit line and the bit line, for electrically separating the sense bit line from the bit line; a sense line to which a signal voltage of the sense bit line is transmitted; a bias circuit connected between the sense line and the sense bit line, for supplying the sense bit line with a specified voltage; a load circuit connected to the sense line; an amplifier circuit supplied with a voltage of the sense line and a reference voltage, for amplifying a difference between both voltages; and a first initialization circuit activated according to a first control signal in the address selection period, for supplying the sense line with a specified voltage.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array having cell-based bit lines and nonvolatile memory cells connected thereto, the nonvolatile memory cell is selected according to address signals in an address selection period; a bit line to which a signal voltage of the cell-based bit line is transmitted; a cell-based bit line decoder circuit for connecting the cell-based bit line in the memory cell array to the bit line in the address selection period according to the address signal; a sense bit line to which a signal voltage of the bit line is transmitted; a separation circuit connected between the sense bit line and the bit line, for electrically separating the sense bit line from the bit line; a sense line to which a signal voltage of the sense bit line is transmitted; a bias circuit connected between the sense line and the sense bit line, for supplying the sense bit line with a specified voltage; a load circuit connected to the sense line; an amplifier circuit supplied with a voltage of the sense line and a reference voltage, for amplifying a difference between both voltages; and a first initialization circuit activated according to a first control signal in the address selection period, for supplying the sense bit line with a specified voltage.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array having cell-based bit lines and nonvolatile memory cells connected thereto, the nonvolatile memory cell is selected according to address signals in an address selection period; a bit line to which a signal voltage of the cell-based bit line is transmitted; a cell-based bit line decoder circuit for connecting the cell-based bit line in the memory cell array to the bit line in the address selection period according to the address signal; a sense line to which a signal voltage of the bit line is transmitted; a bias circuit connected between the sense line and the sense bit line, for supplying the sense bit line with a specified voltage; a load circuit connected to the sense line; an amplifier circuit supplied with a voltage of the sense line and a reference voltage, for amplifying a difference between both voltages; and a first initialization circuit activated according to a first control signal in the address selection period, for supplying the sense line with a specified voltage.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array having cell-based bit lines and nonvolatile memory cells connected thereto, the nonvolatile memory cell is selected according to address signals in an address selection period; a bit line to which a signal voltage of the cell-based bit line is transmitted; a cell-based bit line decoder circuit for connecting the cell-based bit line in the memory cell array to the bit line in the address selection period according to the address signal; a sense line to which a signal voltage of the bit line is transmitted; a bias circuit connected between the sense line and the sense bit line, for supplying the sense bit line with a specified voltage; a load circuit connected to the sense line; an amplifier circuit supplied with a voltage of the sense line and a reference voltage, for amplifying a difference between both voltages; and a first initialization circuit activated according to a first control signal in the address selection period, for supplying the bit line with a specified voltage.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array having cell-based bit lines and nonvolatile memory cells connected thereto, the nonvolatile memory cell is selected according to address signals during an address selection period; a bit line to which a signal voltage of the cell-based bit line is transmitted; a cell-based bit line decoder circuit for connecting the cell-based bit line in the memory cell array to the bit line in the address selection period according to the address signal; a bias circuit connected between a power supply node and the bit line, for supplying the bit line with a specified voltage according to a first control signal; an amplifier circuit supplied with a voltage of the bit line and a reference voltage, for amplifying a difference between both voltages; and a first initialization circuit activated according to a second control signal in the address selection period, for supplying the bit line with a specified voltage.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a bit line to which a read voltage is transmitted from a nonvolatile memory cell storing data; an amplifier circuit having a first and a second input nodes, respectively supplies these first and second input nodes with an input voltage corresponding to a read voltage on the bit line and a reference voltage, for amplifying a difference between both voltages; a bias circuit having a current path inserted between the bit line and the first input node of the amplifier circuit, for supplying a specified voltage to the first input node of the amplifier circuit; and an initialization circuit activated according to a first control signal in the address selection period, for supplying a specified voltage to at least one of both ends of the current path of the bias circuit.
According to the present invention, there is provided a method of controlling a nonvolatile semiconductor memory device in which a bias circuit is operated, thereby setting a data sense node to a prescribed potential in a data sense period, the voltage at the data sense node is changed in accordance with the data read from a memory cell, and an amplifier circuit compares the voltage with a reference voltage in the sense period, thereby sensing the data, the method comprising: setting the data sense node at the prescribed potential by an initialization circuit in the address selection period.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.